1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same. More particularly, the invention relates to semiconductor devices having a bit line plug and methods of fabricating the same.
2. Description of the Related Art
As semiconductor devices are becoming more highly integrated, cell sizes of memory cells are rapidly decreasing. In particular, the high degree of integration in dynamic random access memories (DRAMs) has caused an interval between gate electrodes to be a minimum feature size according to the design rule. Also, as semiconductor devices are becoming more highly integrated, intervals between a contact hole connecting a lower wiring layer with an upper wiring layer and wirings around the contact hole are decreasing. Therefore, when a storage contact hole is formed using a photolithography process in a highly integrated semiconductor device employing a multilayer wiring structure, there are limits to performing a desired process. Accordingly, self-aligned contact (SAC) technology for forming a contact hole using a lower pattern as an etch stop layer is being developed to overcome limitations of the photolithography process. SAC technology may be applied to a storage plug forming process using a bit line pattern as an etch stop layer as well as to a bit line and storage pad forming process using gate patterns as an etch stop layer.
When employing SAC technology, in order to increase a contact area between storage pads and storage plugs of a memory cell, contact holes may be formed to extend below sidewall insulation spacers adjacent to a bit line. Although sidewalls of a bit line plug may be covered with a barrier metal layer, a barrier insulation layer and/or an interlayer insulating layer, during etching, etching solution used to etch the interlayer insulating layer between adjacent bit lines may permeate into an upper portion, e.g., upper edge, of a bit line pad below the bit line plug. For example, in conventional structures, when first and second interlayer insulating layers are isotropically etched, an etching solution may permeate into a bit line pad, thereby modifying a silicide layer that is an ohmic layer. Improved structures and/or methods of fabricating semiconductor devices including bit line plugs are desired.